Senior FPGA / ASIC Verification Engineers at Phoenix

A growing and established Defense/Aerospace Company in the State of Arizona is looking for Sr. FPGA and/or ASIC Verification Engineers. We are looking for candidates nationwide willing to relocate to the Sunny State of Arizona. Once again, these positions are located in Arizona (AZ).

This position will develop and verify FPGA designs for all major vendors and device families including: Xilinx, Altera, Lattice, and Microsemi. The Business Unit also designs digital ASICs and performs obsolescence mitigation activities, including redesign, for digital ASICs. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit designers and systems engineers to develop requirements, architect new parts, partition and perform code development, simulation, place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.

This Business Unit has deployed a Unified Verification Methodology (UVM) based verification capability and is seeking a Senior Verification Engineer to lead all aspects of development, deployment and execution of the Business Units verification strategy. Responsibilities include, but are not limited to:

• Participating in the functional verification of ASICs/FPGAs as-needed


• Leading and mentoring teams of verification engineers


• Creating the verification plan with the Program and RTL designers input and review


• Developing the architecture and design of the environment as well as participating and/or leading a team of engineers to implement the test benches


• Creating the necessary run and/or post-processing scripts

Required Skills for Principal Electrical Engineer:

• Minimum 4-10 years FPGA and/ or ASIC verification experience is required.


• Demonstrated experience and expertise in the following areas is required:


• Creation of verification plans


• Implementation of modern verification environments that include use of constrained-random stimulus and use of functional coverage


• Experience leading a verification team and able to interface to the RTL designer and program/customer as-needed


• Proficient in SystemVerilog


• Experience with one or more of the following: UVM, OVM, eRM, VMM


• Proficient in C/C++


• Proficient in scripting languages and utilities including Make, Perl, Python, Tcl and Shell scripting


• Experience with Questa/ModelSim (preferred), VCS and NCSim (acceptable)


• Development and execution of verification process improvement plans


• Team leadership


• Development and deployment of verification strategies and methodologies across teams and organizations


• FPGA/ASIC design and verification using a Linux based development environment


• Creation of plans, schedules and cost estimates for design verification efforts

Candidates must have broad experience and be expert in the design of FPGAs or ASICs. Must have written VHDL, simulated, synthesized, placed and routed, integrated and tested FPGA/ASIC designs on hardware. Expert level knowledge of simulation tools such as Questa or Incisive, synthesis tools such as Synplify, and back-end tools such as Xilinx ISE, Altera Quartus, or other FPGA vendor tools is required. Candidates must have an understanding and appreciation of technical themes and concepts and the ability to develop solutions independently, but also be able to work with systems engineers, software teams and peers to define requirements.
Demonstrated experience and success in applying best in class design methodologies and tools is required. Working knowledge of Microsoft Office products required.
Country: USA, State: Arizona, City: Phoenix, Company: Kforce Inc.